1. Field of the Invention
The present invention relates generally to minimally packaged semiconductor devices having a protective layer of material on the active surfaces thereof and, more specifically, to the use of stereolithography to fabricate protective layers on the active surfaces of semiconductor device components. More particularly, the invention pertains to a method for fabricating protective structures on at least the active surfaces of semiconductor devices at the wafer level.
2. State of the Art
The large-scale production of particular types of semiconductor devices poses problems peculiar to the type of die, electronic circuits, external connectors and packaging. So-called “flip-chip” dice comprise electronic devices formed on a semiconductor substrate whose integrated circuitry terminates in an array of conductive sites on a die's active surface, which conductive sites are typically referred to as “bond pads.” External conductive structures exemplified by well-known solder “bumps” or “balls” are attached to the bond pads. In use, the flip-chip die is inverted, positioned atop a substrate with contact pads matching the locations of the conductive structures of the die, and the conductive structures bonded to the contact pads of the substrate. Chip scale, flip-chip configured packages are also typically disposed face down over a higher-level substrate with which the chip scale packages are to be connected.
In order to fabricate flip-chip dice in large quantities, several semiconductor dice are simultaneously fabricated on a wafer. The wafer is then scribed or sawn into individual dice, and finishing operations including packaging are conducted on the singulated dice.
It is typically desirable to apply a supportive or protective layer on at least the active surfaces of semiconductor devices, such as flip-chip type dice and chip scale packages, that will be disposed face down over a higher-level substrate. Polymers, glass, and other electrically nonconductive materials can be applied to one or both major surfaces of such semiconductor devices. Conventionally, such layers are applied to a surface of a semiconductor device prior to attaching conductive structures to contact pads exposed at that surface. As the contact pads must be exposed through the layer so conductive structures can be secured to the contact pads, openings must also be formed in the layer to accommodate the subsequent attachment of conductive structures. Thus, an etching or other more complex additional process step is required.
When conventional techniques are employed to form a protective layer on a surface of a semiconductor device, it is difficult to form the protective layer when conductive structures have already been secured to the contact pads because of the close packing and small interstitial spacing between the conductive structures on state of the art semiconductor devices. If introduced onto the surface over the conductive structures, the material of the supportive or protective layer will have to be removed from the conductive structures. If introduced between the conductive structures, air pockets and voids can form in the layer of supportive or protective material.
Moreover, air pockets or voids can form when a so-called “underfill” material is introduced between a semiconductor device and a carrier substrate upon which the semiconductor device is disposed in face down orientation. Although a vacuum may be used to draw the underfill into the interstices between the semiconductor device and the substrate, air pockets and voids nevertheless often persist in the underfill material. Thus, underfill layers with air pockets or voids may not completely support or protect the die or the conductive structures secured to the bond pads thereof. Furthermore, the use of a vacuum introduces undesirable additional complexity and time to the manufacturing process.
Accordingly, there is a need for a process by which supportive or protective layers can be formed on or applied to semiconductor devices without significantly increasing fabrication time and cost while producing a substantially uniform, solid, uninterrupted layer between contact pads of the semiconductor device or conductive structures secured thereto.